This invention relates to digital signal processing, and more specifically to an adaptive digital filter architecture which performs tap updating in an efficient manner.
A proposed technology for providing DS1-rate (1.544 mb/s) transmission over the customer serving area portion of the copper twisted-pair telephone loop plant is known as the High Speed Digital Subscriber Line (HDSL) (see, e.g., B. A. Mordecai, T. R. Hsing, D. L. Waring, and D. S. Wilson, "Repeaterless technology brings copper and fiber together," Telephony, Jul. 2, 1990, pp. 28-33.) The initial targeted application for HDSL is a non-repeatered, POTS(plain old telephone service)-like deployed, DS1 service. DS1 service over the copper plant is currently provided by T1 carrier, a technology which may require costly engineering effort and service initialization delays. Provided that the cost of HDSL electronics is sufficiently low, service providers could use HDSL technology to supplant T1 carrier in providing new DS1 orders.
One of the most crucial components of an HDSL transceiver is the adaptive channel equalizer. The extreme high frequency rolloff of HDSL channels, and the intersymbol interference (ISI) which this rolloff produces, must be countered by an equalizer at the receiver. The wide range of channel characteristics present within the copper loop plant, and the tendency of any given channel to change slowly with time, require the channel equalizer to be adaptive. Since channel equalizers are typically implemented as one or more digital filters, the success of HDSL is dependent upon the availability of low-complexity, yet computationally powerful, adaptive digital filter architectures.
As is well known in the digital filter art, an adaptive finite impulse response (FIR) digital filter processes an input signal by multiplying a current digital input signal value and the input signal value at plural equally spaced discrete previous time instants, with a set of tap coefficient values which are continually being updated. The current input signal value and the previous input signal values as multiplied by their corresponding tap coefficient values and are then summed to produce an output signal. The difference between the resultant output signal and a desired signal value, is an error signal which is used to adapt and update the coefficient values of the FIR filter structure for calculation of the filter output at a subsequent time instant or instants. By constantly updating the tap coefficient values, the filter is able to adapt to external environmental factors such as changing signal conditions over the receiving data channel.
Prior art adaptive digital filters have used various algorithms for updating the tap coefficients. One of the most popular algorithms is the LMS, or stochastic gradient algorithm, and the variants thereof. In accordance with each of these algorithms, each tap coefficient in the filter structure is updated by a prescribed mathematical formula that is a function of that tap's previous coefficient value, the error signal and a previous signal value in that tap.
Generally, prior art adaptive FIR filter implementations are structured to calculate the filter output (and also error) from the sum of products (SOPs) of tap coefficients times delayed input values, and to then compute, for each tap from the error obtained in the first step, the tap's updated coefficient to be used in calculating the filter output at a subsequent time instant. This serial approach has two significant disadvantages. The first is that each data element (present and previous input values) and tap coefficient value must be fetched twice from memory: once in forming the FIR SOPs calculation, and once in performing the tap updates. Depending on the hardware implementation, precious machine cycles may be wasted as a result of this dual fetch thereby limiting the speed at which the filter can operate. The second disadvantage is that in applications whose processing throughput calls for the use of two processors to perform the calculations (e.g., applications where filter length or input/output speed requires more than one processor), the serial approach requires that the FIR SOPs calculation be distributed between the two processors. Additional hardware and one or more overhead machine cycles are then required to add the partial SOPs to form the filter output.
An object of the present invention is to avoid the aforenoted disadvantages of the serial approach of the prior art with an alternative digital filter architecture.